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Design experience (verilog)
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* Servo controller - my largest individual design was a
servo block for a
hard disk controller. This was completely programmable for any servo
pattern and encoding.
It had some programmable error detection
and correction built-in, depending on the encoding. It worked with any
read
channel. I designed a very clever fast data synchronizer that
sampled the read channel data on both clock edges and
self-adjusted to
jitter and motor errors based on the expected timing.
* Processor bridges - in order to be able
to give customers a choice of
processor (ARM7/ARM9/ARC/MIPS4k/etc), or even the ability to swap
processors (for benchmarking
and/or leverage when negotiating w/ processor
companies), I created a generic processor interface. I then designed many
of
the inidividual processor bridges (ARM7/ARM9/ARC - started MIPS4k &
Tensilica before passing them off) which essentially
translated their
unique memory bus signals into the generic i/f.
* USB 1.1 - created wrapper around InSilicon's
USB device core to make it
system-friendly and integrated it into our CoreFrame architecture. By
system-friendly,
I mean creating registers out of their mess of dangling
status/control signals, working out interrupt conditions, and designing
a
DMA interface.
* P1284 - Designed parallel port i/f block. Handled all modes
(compatible/byte/nibble/ecp/epp)
with selectable FIFOs and/or DMA.
* DFT - At Virage, I worked closely with the developers of their embedded
memory
test blocks. I also had the joy of helping customers integrate the
embedded test and repair sub-system into their
systems. So my expertise
in verilog, simulation, synthesis, and other system issues was not just
going stale at
Virage.
Testbench & code generation
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* I created a pre-processor language
that made it very easy to write
configurable code. I then used it to start automating our code and
testbench generation
for new blocks. All you had to provide was a
parameter file with your register and bit definitions, and out would
come
the PalmBus interface block, a verilog testbench (that called bus
functional model tasks, allowing us to use the
same test at both the block
and the system level), and the C header file. It was also going to
generate the C
register read/write test, but I didn't have time to finish
that, as this was all done in parallel with other projects and
responsibilities.
The pre-processor parser I wrote was written in Perl,
and I designed it such that you could actually embed Perl in your
configurable
code, making it as powerful or simple as the designer wanted.
Software experience
-------------------
* Wrote
C modules and tests for various blocks in SOC. Palmchip provided
embedded software as well as hardware for all of our designs.
This
included boot code and interrupt handling routines for specific
processors, as well as the APIs for individual
blocks. The code would be
compiled and the object code loaded into the memory models. The processor
was
either a C model, bus functional model, or the actual verilog code.
Again, while I wasn't a firmware engineer, it was a
small company and I
often wrote code just to get it done.
* At Kiva Software, where I was an intern for one month
before being
promoted to software engineer for the rest of the summer and into my
school year, our server was written
in C++ while all the client-side apps
were written in Java. I wrote both sides of the admin tool, which
included
a file transfer protocol between the two (something you would
never have to do today, but this was Java 1.0, which didn't
have many
built-in or available libraries at the time).
* I wrote a commercial program under contract from Associated
Students of
Stanford Univ and Stanford Student Enterprises that handled cutting refund
checks for ASSU fees. Students
logged into a website, submitted data
about what fees they wanted refunded, and once per quarter the ASSU cuts
checks.
This program was written in C++ for MacOS. It read in data
generated by the cgi scripts, and student registration
data from the
Registrar's office, and then printed checks, generated reports, and stored
data for use in upcoming quarters.
*
I have a CS minor from Stanford, which required projects in several
programming languages, including large C++ projects.
EDA
Tools
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Verilog-XL, NC Verilog, Signalscan, Virsim, Synopsys Design Compiler and
PrimeTime, Synplicity, Altera's
Quartus, Calibre DRC/LVS
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